1. Field of the Invention
The present invention generally relates to a method for staining a sample as well as a sample cross-section which is obtained from sampling a test device in a special way. In particular, the present invention is directed to a method for staining a sample by means of two independent staining procedures as well as a sample cross-section obtained thereby.
2. Description of the Prior Art
Integrated circuits are essential components of various electronic products such as micro-electro-mechanical devices (MEMS), CPUs, processors, memories, and so on. Integrated circuits are usually fabricated by standard semiconductor processes involving silicon wafer fabrication techniques.
A standard semiconductor process usually involves many procedures, such as deposition, lithography, etching, chemical and mechanical polishing and implantation . . . etc. After the procedures, the integrated circuits have to be subjected to various tests to ensure that the fabrication procedures have produced operative devices. There may be many reasons why a device does not operate correctly. One of these could be a failure in the device itself due to procedure reasons. If the failure is found to be in the device and recurs frequently in devices made by the same procedure, this could indicate that this manufacturing procedure needs to be further adjusted in order to correct or prevent the errors.
For example, doping regions are expected to form within the substrate and develop a correct profile, providing the semiconductor wafer has been subject to an ion implantation procedure to construct such doping regions. One cause of failure in a device can occur in the doping profile of a substrate which has been subject to an implantation procedure. The doping profile in the substrate deviates from where it is required, which can lead to current leakage and at the same time cause the device to malfunction. For example, the junction profile in an SRAM device, and especially the junction profile of the active area (AA) in a PMOS, is of great interest since the shape of the active area (AA) in the PMOS of an SRAM device may be irregular: a curved shape for instance.
Because the junction profile should be formed within the substrate and surrounded by a less-doped substrate, an incorrect doping profile of the substrate cannot be easily detected using microscopy as different doping profiles in the substrate provide no contrast to the surrounding substrate and therefore cannot be visually distinguished.
One current method which is widely used to visualize the substrate implantation defects is to cut a piece of sample from the device. FIG. 1 illustrates how a piece of sample is cut along the line A-A in order to expose the junction profile in the conventional method. The device 10 is illustrated as an SRAM. The device 10 has a PMOS region 11 and an NMOS region 12. Please note that the active area 13 of the PMOS region 11 has a croissant shape, compared with the NMOS region 12.
Later, the sample is subject to a staining procedure to stain the target regions, i.e. the doped regions, by means of a single chemical solution. This is called a junction delineation or junction stain, which delineates areas with different doping levels so as to make the fail sites visible. Staining delineates the various layers and provides better contrast for examining the device using an SEM (Scanning Electron Microscope).
Since the chemical solution is so formulated to focus on the target regions only, the sample must be overcut into the entire active area 13 so that the junction profile within the active area 13 can be totally exposed. Line A-A in FIG. 1 indicates the overcut of the sample to totally expose the junction profile within the active area 13.
Because the critical dimension of the device 10 is downsized, the area of the active area 13 is downsized too, which makes it increasingly hard to obtain a correctly cut and stained sample; in particular, for the active area 13 of the PMOS region 11 of the croissant shape. In view of the above, it is understood that the conventional junction staining method suffers from a controllability problem since the extent of overcut is critical. If it is undercut, the junction profile within the active area 10 cannot be totally exposed, and the chemical solution is therefore not able to develop a good stain profile. If it is too overcut, however, there would be an insufficient junction profile left for the staining procedure. Furthermore, it is also very difficult to obtain a sample which is neither undercut nor too overcut. As a result, a novel method is still needed for staining a sample to overcome the aforesaid problems.